spi: aspeed: Respect transfer-specific bit width#5
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The ASPEED SPI driver previously configured the controller's transfer mode (dual, quad, or single) based globally on the target device's capability flags (spi->mode & SPI_TX_DUAL/QUAD), ignoring the requested width of individual transfers in the message sequence. This deviates from the Linux SPI subsystem design, which expects command, address, and dummy phases of a transaction to default to single-bit transmission, with multi-bit mode restricted strictly to the data payload transfers that request it via tx_nbits or rx_nbits. Fix this by dynamically adjusting the controller's IO mode for each transfer segment. The dual or quad IO mode is activated only if both the individual transfer requests the multi-bit width (tx_nbits/rx_nbits) and the device globally supports that mode (spi->mode). All other transfers remain in the default single-bit mode.
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Hi @mfield4, Thanks for the patch — the intent is correct, and we appreciate you spotting this issue. We have a fix for this queued in our internal tree with a slightly different approach. if (xfer->tx_nbits == SPI_NBITS_DUAL)
ctrl_val |= SPI_DUAL_IO_MODE;
else if (xfer->tx_nbits == SPI_NBITS_QUAD)
ctrl_val |= SPI_QUAD_IO_MODE;The additional Checking We'll carry our version of this fix in our upcoming update, so we won't be merging this PR. |
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Hi @hung-chu-huang, I let this slip under the radar a bit, so this is a welcome surprise coming in this morning. I appreciate the attribution, and will close the PR. Thank you so much! |
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The ASPEED SPI driver previously configured the controller's transfer mode (dual, quad, or single) based globally on the target device's capability flags (spi->mode & SPI_TX_DUAL/QUAD), ignoring the requested width of individual transfers in the message sequence. This deviates from the Linux SPI subsystem design, which expects command, address, and dummy phases of a transaction to default to single-bit transmission, with multi-bit mode restricted strictly to the data payload transfers that request it via tx_nbits or rx_nbits.
Fix this by dynamically adjusting the controller's IO mode for each transfer segment. The dual or quad IO mode is activated only if both the individual transfer requests the multi-bit width (tx_nbits/rx_nbits) and the device globally supports that mode (spi->mode). All other transfers remain in the default single-bit mode.